Training vs Inference Optimization Trade-offs Questions
Covers the trade-offs between training and inference phases in machine learning systems, including strategies to optimize for both sides. Topics include training efficiency (data utilization, convergence, hyperparameter tuning), inference performance (latency, throughput, memory footprint), deployment considerations (model compression, quantization, pruning, distillation), hardware acceleration, serving architectures (online vs batch), update and versioning strategies, and cost-performance modeling in production ML pipelines.
HardTechnical
89 practiced
Discuss complexities when combining mixed-precision training with model parallelism and gradient checkpointing at scale. Cover memory fragmentation, communication overhead, numerical stability, and tuning knobs you would expose to balance them. Provide remedies for common failures in large-scale jobs.
Sample Answer
Combining mixed-precision, model parallelism, and gradient checkpointing at scale introduces interacting trade-offs across memory, communication, and numerical stability. Below I outline key complexities, tuning knobs to expose, and practical remedies for common failures.Complexities- Memory fragmentation: mixed-precision reduces footprint but allocator fragmentation (many short-lived tensors from activation recompute and sharded parameters) can leave unusable GPU memory, causing OOMs despite headroom.- Communication overhead: model parallelism (pipeline/tensor parallelism) increases synchronization (all-reduce, send/recv) that can dominate wall-clock time when activation recompute reduces computation-to-communication ratio.- Numerical stability: FP16/BF16 accumulate rounding and dynamic range issues; checkpointing changes compute order (recompute gradients) affecting rounding paths and sometimes causing NaNs or exploding grads.- Checkpointing interaction: recompute increases peak temporary memory reuse patterns and CPU-GPU transfer if offloading is used; it also lengthens critical path, amplifying stragglers.Tuning knobs to expose- Precision controls: global dtype (bf16/fp16) + selective fp32 cast whitelist for layernorm, softmax, and loss-scaling points.- Loss scaling: static vs dynamic, initial scale, growth/decay factors, and overflow recovery thresholds.- Checkpoint granularity: per-layer, per-block, or custom chunks to trade compute vs memory and to control recompute overhead.- Placement and shard sizes: tensor-slice sizes for tensor-parallel sharding, pipeline micro-batch size, and CPU/GPU offload thresholds.- Communication scheduling: fused vs unfused all-reduce, overlap degree, and NCCL/RDMA tuning (ring vs hierarchical).- Allocator parameters: arena fragmentation thresholds, pooling strategies, and delayed free windows.Remedies for common failures- Persistent OOM despite apparent memory: enable memory defragmentation (cache trimming), reduce fragmentation by using pooled allocator flags, increase checkpoint chunk size, or move small tensors to CPU until stable. Try different CUDA allocator (jemalloc-like) or PyTorch empty_cache() strategically in between phases.- Excessive communication stalls: increase computation-to-communication ratio (larger local batch, fewer pipeline stages, fuse all-reduces), enable async op overlap, or use hierarchical all-reduce (node-local then cross-node).- NaNs/instability: switch sensitive ops to fp32 (LayerNorm, softmax, attention scaling), lower learning rate, enable dynamic loss scaling, clamp gradients, or use scaled optimizer states (FP32 master weights with FP16 params). Run FP32 warmup steps then switch to mixed precision.- Slow jobs/stragglers under checkpointing: rebalance micro-batches, reduce recompute depth, or use activation offload to CPU for long-lived activations. Profile and adjust pipeline bubble filling.- Reproducibility divergence: fix deterministic cuDNN/path settings, control random seeds, and be aware recompute may change numeric sequences.Practical workflow1. Start with BF16 if hardware supports it; use FP32 master weights.2. Enable dynamic loss scaling and selective FP32 ops.3. Tune checkpoint granularity until memory fits with acceptable runtime.4. Profile communication; switch to fused/hierarchical collectives and overlap where possible.5. Monitor for NaNs—if seen, escalate ops to FP32 or reduce loss scale/gain warmup.6. Use automated health checks (memory, gradient norms, communication rates) and fallbacks (reduce parallelism or batch size) to recover at runtime.Balancing these knobs while iteratively profiling (nvprof/Nsight, NCCL counters, framework traces) is essential—aim for stable numeric behavior first, then optimize throughput, and use conservative defaults for production large-scale runs.
MediumTechnical
83 practiced
Provide a script outline (pseudo-code or short Python) using PyTorch to apply dynamic quantization to an LSTM-based model and a plan to validate that accuracy drop is acceptable. Include steps for preparing calibration data, applying quantization, and running evaluation.
Sample Answer
Approach: use PyTorch dynamic quantization (works well for LSTM/linear-dominated models) to reduce model size and latency. Prepare representative calibration/eval data, apply torch.quantization.quantize_dynamic, then evaluate accuracy and latency versus baseline; accept if accuracy drop within threshold (e.g., <=1%) and latency/size gains meet targets.Python outline:Validation plan:- Metrics: accuracy (or BLEU/F1 for seq tasks), throughput (samples/sec), latency (p99), model size.- Acceptance criteria: e.g., accuracy drop <= 1% absolute (or relative), latency improvement >= X% or size reduction >= Y%.- Statistical rigor: run N independent runs, compute mean±std; if close to threshold, run A/B test on live traffic or larger holdout.- Edge cases: variable-length sequences, packed sequences—ensure quantized model supports your input pipeline; compare on same hardware/config.- If accuracy drop too large: try selectively excluding sensitive layers from quantization, use float16 mixed precision, or per-channel/static quantization for parts of model.
python
import torch
from torch.utils.data import DataLoader
# 1. Load model and weights
model = MyLSTMModel(...) # contains nn.LSTM, nn.Linear
model.eval()
baseline = model # keep baseline copy
# 2. Prepare calibration / eval dataset (representative)
calib_loader = DataLoader(calib_dataset, batch_size=32, shuffle=False)
eval_loader = DataLoader(eval_dataset, batch_size=32, shuffle=False)
# 3. Apply dynamic quantization
quantized_model = torch.quantization.quantize_dynamic(
model, {torch.nn.LSTM, torch.nn.Linear}, dtype=torch.qint8
)
# 4. Evaluation function
def evaluate(m, loader):
m.eval()
total, correct = 0, 0
import time
t0 = time.time()
with torch.no_grad():
for x, y in loader:
out = m(x)
pred = out.argmax(dim=-1)
correct += (pred == y).sum().item()
total += y.numel()
latency = (time.time() - t0) / len(loader)
return correct/total, latency
# 5. Run evals
acc_baseline, lat_base = evaluate(baseline, eval_loader)
acc_q, lat_q = evaluate(quantized_model, eval_loader)
# 6. Size
import io
def model_size(m):
f = io.BytesIO(); torch.save(m.state_dict(), f); return f.getbuffer().nbytes
size_base, size_q = model_size(baseline), model_size(quantized_model)
print(acc_baseline, acc_q, lat_base, lat_q, size_base, size_q)MediumTechnical
95 practiced
You must reduce a 200MB model to fit a 50MB mobile budget while keeping accuracy drop under 2%. Compare pruning-first vs distillation-first strategies and recommend a plan that considers engineering time, expected runtime improvements on commodity mobile hardware, and validation on-device.
Sample Answer
Short answer: start with distillation to preserve accuracy, then apply structured pruning and quantization — iterate with on-device validation. This balances accuracy preservation, engineering effort, and real-world runtime gains.Compare strategies:- Pruning-first: remove weights/filters from the 200MB model to hit 50MB. Pros: immediate model-size reduction; structured pruning (filter/channel) can reduce FLOPs and latency on mobile. Cons: pruning often degrades accuracy nonlinearly and requires costly fine-tuning; reaching 4x compression from 200→50MB likely harms accuracy >2% unless carefully tuned. Engineering time: moderate-to-high for iterative pruning schedules, re-training, and compiler/tooling to exploit sparsity. Runtime improvements: structured pruning yields decent latency gains; unstructured sparsity rarely helps on commodity mobile CPUs without specialized sparse kernels.- Distillation-first: train a smaller student (architectural downscale or parameter-efficient network) using teacher logits. Pros: preserves accuracy better, more predictable; student can be designed to map to efficient mobile blocks (MobileNetV3, efficient Transformers). Engineering time: moderate (design/ train student), faster convergence to target accuracy. Runtime improvements: student architectures + post-training quantization give reliable real-device speedups.Recommended plan:1. Define constraints & metrics: 50MB, <2% accuracy drop, target P95 latency, energy budget.2. Distillation phase: - Design student around efficient blocks sized ~40MB to leave room for quantization/overhead. - Use soft-label distillation + auxiliary losses (feature-map hints) for stability. - Train with mixed precision, early stopping on validation delta.3. Compression phase: - Apply structured pruning (channel/filter) to remove redundant blocks if size still >50MB. - Use magnitude/learned importance with one-shot or gradual pruning and short fine-tune.4. Quantization: - Post-training static quantization (8-bit) or QAT if accuracy loss >1%.5. On-device validation (continuous): - Deploy APK with instrumentation to sample latency, memory, and accuracy on representative devices. - Run A/B tests across device classes (low-end CPU, mid-tier, flagship). - Measure end-to-end metrics (latency, RSS, battery, top-k accuracy) and iterate.Expected outcomes:- Engineering timeline: 3–6 weeks (distillation 1–3w, pruning+QAT 1–2w, on-device testing 1–2w).- Runtime: well-designed student + 8-bit quantization typically gives 3–6x speedup vs original on CPU; structured pruning can add another 10–30% depending on architecture.- Risk mitigation: prioritize distillation to meet accuracy target, use pruning only to squeeze final bytes, and validate on-device early & often.
HardSystem Design
106 practiced
Design an end-to-end real-time ML pipeline that meets strict SLOs for personalization (e.g., P95 inference latency < 150ms) including: event ingestion, streaming feature computation, online feature store, model serving, caching, and cold-start handling. Describe how to ensure feature consistency between training and serving and how to handle high-cardinality features at low latency.
Sample Answer
Requirements:- P95 inference latency <150ms, throughput up to X qps, strong feature consistency training↔serving, support streaming user events, low-latency lookup for high-cardinality features, robust cold-start.High-level architecture:Event producers → Ingestion (Kafka/KSQ) → Stream processors (Flink/Beam) → Online Feature Store (Redis/Key-Value NVMe + RocksDB) + Offline store (Parquet in S3 + OLAP) → Model Serving (GRPC microservice with batching + GPU/CPU pool) → Cache (L1 in-process + L2 Redis) → Monitoring & Control Plane.Components & responsibilities:- Ingestion: Kafka for durable, ordered events; compacted topics for user state.- Streaming feature computation: Flink/Beam compute windowed, incremental aggregates and write materialized state to online store with exactly-once sinks. Use event-time semantics and watermarking.- Online feature store: Low-latency KV store keyed by user-id or entity (sharded). Store versioned feature blobs with schema/version metadata and timestamps.- Model serving: Stateless servers load model + feature transform code; request flow: lookup features (L1 cache hit -> local memory, else L2 Redis -> feature hydration) then inference. Use async I/O, small request batching, and concurrency limits to meet latency SLO.- Caching: L1 per-process (hot users), L2 Redis with TTL and negative-cache marker for missing.- Cold-start: Use heuristic defaults + similarity-based fallbacks (population averages, cluster-level features, recent cohort embeddings). Fall back to lightweight model when features missing.- High-cardinality features: Precompute dense embeddings offline/streaming (user/item embeddings) and store them in online store; use approximate nearest neighbor indexed externals for similarity. For categorical high-cardinality keys, store hashed compressed vectors or use product quantization to reduce size and lookups. Use bloom filters to avoid unnecessary remote lookups.- Feature consistency training↔serving: Unify feature definitions in a single Feature Registry (schema, transform code, version). Use the same streaming transforms runnable in batch for training (Flink/Beam + Spark with portable UDFs). Materialize training features from the same offline store built from Kafka via replay to reconstruct exact feature snapshots at training time. Persist feature version & timestamp with each training example and embed feature spec into model metadata. At serving time, the feature lookup enforces version compatibility; reject requests if required version not present.- Latency/SLO strategies: Keep network hops minimal, colocate Redis in same AZ, use hot caches, circuit breakers, adaptive batching, CPU/GPU autoscaling with predictive autoscaler. Measure tail latency with distributed tracing and SLO alerts.- Reliability & correctness: Exactly-once processing, idempotent writes, monitor feature drift, data quality checks, canary deploys for model changes, shadow serving for validation.Trade-offs:- Strong consistency + exactly-once increases processing cost; mitigate by tiering features (strict vs eventual) so critical features use stronger guarantees.This design provides end-to-end low-latency personalization while ensuring training-serving consistency and scalable handling of high-cardinality features.
MediumTechnical
75 practiced
Explain operator fusion and kernel-level optimizations in inference runtimes. Describe how fusing operations (e.g., conv+bn+relu or matmul+add) affects memory bandwidth, cache locality, and latency, and discuss scenarios where fusion might actually degrade performance.
Sample Answer
Operator fusion is the practice of combining multiple adjacent graph operators into a single kernel so computations and data movement between them happen without round-trips to main memory or separate kernel launches. Common fusions: conv+batchnorm+relu, matmul+bias+gelu, or sequences of pointwise ops.Why fusion helps- Memory bandwidth: Fusion eliminates intermediate tensors written to and read from DRAM, reducing memory traffic. For memory-bound ops (e.g., convs on small batch sizes), this can be the dominant win.- Cache locality: Keeping producer/consumer data in registers or L1/L2 caches improves reuse and reduces cache thrashing — fewer cache lines loaded/stored.- Latency and kernel launch overhead: Fewer kernels mean fewer launches (important on GPUs/TPUs) and lower end-to-end latency. A fused kernel can also expose instruction-level and SIMD/WARP-level parallelism, improving throughput.Concrete example- conv + BN + ReLU: Instead of conv -> write output -> BN (read) -> write -> ReLU (read/write), a fused kernel computes conv outputs, immediately applies BN (using precomputed scale/shift) and applies ReLU before emitting the final tensor. Memory traffic drops by roughly the size of intermediate tensors; kernel launches reduce from three to one.When fusion can degrade performance- Register pressure and spilling: Fused kernels can require more registers per thread. If register usage exceeds hardware limits, spill to local memory increases latency and memory traffic, negating benefits.- Reduced parallelism / occupancy: Larger kernels may serialise work that would otherwise be parallel across CUDA blocks or vector lanes, lowering occupancy and throughput on massively parallel hardware.- Poor auto-tuning and specialization: Separate kernels allow runtime/autotuners to pick optimal algorithms per op (e.g., Winograd conv) or tiling sizes. A fused generic kernel may miss those per-op optimizations.- Small or heterogeneous inputs: For very small tensors, the overhead of a more complex fused kernel can outweigh savings. For mixed precision/quantized pipelines, fusion may complicate numeric handling and force conservative casts.- Reuse and caching trade-offs: If an intermediate is reused by multiple consumers, fusing the producer with one consumer prevents reuse and may force recomputation or extra copies.- Maintainability and debugging: While not a runtime perf issue per se, very aggressive fusion complicates profiling and debugging; engineers may avoid it, slowing iteration.Best practice- Fuse pointwise chains and producer-consumer chains where intermediates are not reused and register pressure/occupancy stay within hardware limits.- Use hardware-aware autotuning and profile both fused and unfused variants; choose fusion heuristics that consider register usage, occupancy, data layout, and whether specialized kernels exist for sub-ops.- For production inference, combine static compilation fusion with runtime checks (batch size, dtype) to pick the optimal kernel.
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