Firmware Buffering & Ring Buffers Questions

Low-level data movement and buffering in constrained systems: circular/ring buffers, producer-consumer queues, lock-free single-producer/single-consumer designs, and handling overflow and wraparound. Covers buffering strategies for streaming data between ISRs, DMA, and application code without dynamic allocation.

MediumTechnical

69 practiced

In C, implement a compact ring buffer API suitable for an embedded RTOS where producers may run in ISR context and consumers run in task context. The ring buffer stores uint8_t values. Provide the struct definition and implementations for: bool rb_push_from_isr(ringbuf_t *rb, uint8_t b); bool rb_pop_blocking(ringbuf_t *rb, uint8_t *b, TickType_t timeout); Constraints: producer runs in ISR and must not call blocking RTOS APIs; consumer may block; avoid dynamic allocation; target single-core Cortex-M; assume 32-bit atomic read/write for indices. Also briefly explain why your approach is safe.

Sample Answer

Approach (brief) Use a power-of-two sized circular buffer with 32-bit head/tail indices (volatile). Producers in ISR update head only after writing the byte (write barrier) and notify the consumer using an RTOS from-ISR notify (semaphore/notify handle stored in struct). Consumer runs in task context and blocks on the RTOS primitive when buffer empty. Single-core Cortex-M + 32-bit atomic index read/writes make this lock-free and safe without disabling interrupts. Struct and implementation: c#include <stdint.h> #include <stdbool.h> #include "FreeRTOS.h" #include "semphr.h" typedef struct { uint8_t *buf; // buffer memory (size = 2^power) uint32_t mask; // size - 1 volatile uint32_t head; // next write index volatile uint32_t tail; // next read index SemaphoreHandle_t notify; // created statically by caller; used for consumer wake } ringbuf_t; /* ISR-safe push: returns true if pushed; must be called from ISR context. Does not block. Calls xSemaphoreGiveFromISR if notify != NULL. */ bool rb_push_from_isr(ringbuf_t *rb, uint8_t b) { uint32_t head = rb->head; uint32_t next = (head + 1) & rb->mask; uint32_t tail = rb->tail; /* atomic 32-bit read */ if (next == tail) { return false; /* full */ } rb->buf[head] = b; /* compiler/CPU barrier to ensure byte is visible before index update */ __asm volatile ("" ::: "memory"); rb->head = next; /* publish new data */ if (rb->notify) { BaseType_t xHigherPriorityTaskWoken = pdFALSE; xSemaphoreGiveFromISR(rb->notify, &xHigherPriorityTaskWoken); portYIELD_FROM_ISR(xHigherPriorityTaskWoken); } return true; } /* Blocking pop: waits up to timeout ticks. Returns true and writes *b on success. */ bool rb_pop_blocking(ringbuf_t *rb, uint8_t *b, TickType_t timeout) { for (;;) { uint32_t tail = rb->tail; uint32_t head = rb->head; /* atomic read */ if (tail != head) { *b = rb->buf[tail]; __asm volatile ("" ::: "memory"); rb->tail = (tail + 1) & rb->mask; return true; } /* empty: wait for notify or timeout */ if (rb->notify == NULL) { /* no notify available: poll with yield */ if (timeout == 0) return false; vTaskDelay(1); if (timeout != portMAX_DELAY) timeout--; } else { if (xSemaphoreTake(rb->notify, timeout) != pdPASS) return false; /* loop to consume any available bytes */ timeout = 0; /* after wake, don't wait further */ } } } Why this is safe Single-core Cortex-M + 32-bit aligned index reads/writes are atomic: head/tail updates won't tear. Producer (ISR) writes data first, issues a compiler barrier, then updates head — consumer will never read uninitialized byte. Consumer reads head before reading buffer and advances tail after reading — avoids races. No blocking or RTOS API calls in the ISR other than FromISR variants. notify semaphore lets consumer block efficiently; buffer size must be power-of-two and allocated by caller (no dynamic alloc inside).

HardTechnical

80 practiced

Implement a lockless single-producer (ISR) / single-consumer (main) circular buffer in C for passing variable-length messages. Constraints: single-core 32-bit MCU (32-bit reads/writes are atomic), no mutexes or atomics, minimal RAM overhead, and handle wrap-around. Provide code for enqueue_from_isr and dequeue_in_thread and explain memory ordering concerns.

Sample Answer

Approach (brief) Use a power-of-two buffer with head (producer write index) updated only by ISR and tail (consumer read index) only by thread. Use 32-bit atomicity guarantee for reads/writes. Store message length (uint32_t) before payload. Enqueue fails if not enough contiguous space; handle wrap by inserting a zero-length padding header to skip to buffer start. c#include <stdint.h> #include <string.h> #include <stdbool.h> #define BUF_SIZE 1024 // power of two #define MASK (BUF_SIZE - 1) static uint8_t ring[BUF_SIZE]; static volatile uint32_t head = 0; // written by ISR static volatile uint32_t tail = 0; // written by thread // write from ISR: returns true on success bool enqueue_from_isr(const void *msg, uint32_t len) { uint32_t h = head; // local copy uint32_t t = tail; // read tail (updated by thread) uint32_t used = h - t; uint32_t free = BUF_SIZE - used; uint32_t need = sizeof(uint32_t) + len; if (need > free) return false; uint32_t pos = h & MASK; // if remaining linear space is insufficient for header+payload, add padding uint32_t linear = BUF_SIZE - pos; if (linear < sizeof(uint32_t)) { // write zero-length header as padding *(uint32_t *)&ring[pos] = 0; h += linear; pos = 0; } // write header *(uint32_t *)&ring[pos] = len; pos = (pos + sizeof(uint32_t)) & MASK; // write payload (may wrap) uint32_t first = (len <= BUF_SIZE - pos) ? len : (BUF_SIZE - pos); memcpy(&ring[pos], msg, first); if (first < len) memcpy(&ring[0], (const uint8_t*)msg + first, len - first); // publish new head (32-bit write is atomic) head = h + need; return true; } // dequeue in thread: returns length copied to buf, 0 if no message uint32_t dequeue_in_thread(void *buf, uint32_t maxlen) { uint32_t t = tail; uint32_t h = head; // read head (updated by ISR) if (t == h) return 0; // empty uint32_t pos = t & MASK; uint32_t hdr = *(uint32_t *)&ring[pos]; if (hdr == 0) { // padding, skip to start t += (BUF_SIZE - pos); pos = 0; hdr = *(uint32_t *)&ring[0]; } uint32_t len = hdr; if (len > maxlen) return 0; // too big for caller buffer (could return error) pos = (pos + sizeof(uint32_t)) & MASK; uint32_t first = (len <= BUF_SIZE - pos) ? len : (BUF_SIZE - pos); memcpy(buf, &ring[pos], first); if (first < len) memcpy((uint8_t*)buf + first, &ring[0], len - first); tail = t + sizeof(uint32_t) + len; return len; } Memory-ordering notes On a single-core 32-bit MCU, 32-bit aligned reads/writes are atomic; head/tail are 32-bit. Producer (ISR) only writes head; consumer only writes tail — no locks needed. Must ensure compiler doesn't reorder accesses: declare head/tail volatile and avoid optimizing assumptions. If CPU has weak memory model (rare in single-core MCUs), use a compiler barrier or memory barrier around the publish of head in ISR and around reading head in thread (e.g., asm volatile("" ::: "memory")). Write payload before publishing head; consumer reads head first, then payload. Padding header (zero) prevents consumer from misreading a split header across wrap. Edge cases Max message size < BUF_SIZE - sizeof(uint32_t) ISR must be short; memcpy can be optimized or replaced with DMA if heavy. Ensure BUF_SIZE power-of-two for mask arithmetic.

MediumTechnical

87 practiced

Write a C implementation of a fixed-size circular byte buffer with power-of-two capacity. Requirements: target ARM Cortex-M, single-producer single-consumer (SPSC) semantics where the producer runs in an ISR and the consumer in the main loop. Operations must be non-blocking and interrupt-safe without disabling interrupts. Provide functions: void rb_init(uint8_t *buf, size_t size), bool rb_push(uint8_t b), bool rb_pop(uint8_t *out). Document any memory-ordering or 'volatile' usage assumptions you make.

Sample Answer

Approach Use power-of-two capacity so index wrap is mask = size - 1. Keep head (read index) and tail (write index) as unsigned integers that monotonically increase; buffer index = idx & mask. For ARM Cortex‑M (single core, byte store/read atomic), use volatile for head/tail and memory ordering via compiler barriers (asm volatile("" ::: "memory")) to prevent reordering between producer (ISR) and consumer (main). No interrupt disabling. c#include <stdint.h> #include <stddef.h> #include <stdbool.h> struct rb { uint8_t *buf; size_t mask; // size - 1 volatile uint32_t head; // consumer reads volatile uint32_t tail; // producer writes }; static struct rb rb_inst; void rb_init(uint8_t *buf, size_t size) { // size must be power of two rb_inst.buf = buf; rb_inst.mask = size - 1; rb_inst.head = rb_inst.tail = 0; } /* Compiler memory barrier to prevent reordering */ static inline void barrier(void) { asm volatile ("" ::: "memory"); } bool rb_push(uint8_t b) { uint32_t tail = rb_inst.tail; uint32_t head = rb_inst.head; /* read consumer index */ uint32_t next = tail + 1; if ((next - head) > (rb_inst.mask + 1)) return false; /* full */ rb_inst.buf[tail & rb_inst.mask] = b; barrier(); /* ensure data written before updating tail */ rb_inst.tail = next; return true; } bool rb_pop(uint8_t *out) { uint32_t head = rb_inst.head; uint32_t tail = rb_inst.tail; /* read producer index */ if (head == tail) return false; /* empty */ *out = rb_inst.buf[head & rb_inst.mask]; barrier(); /* ensure read completes before advancing head */ rb_inst.head = head + 1; return true; } Explanation & Assumptions SPSC: producer only writes tail and buffer slot; consumer only writes head. volatile prevents compiler caching of head/tail. The memory barrier prevents compiler (and on ARM, typical out-of-order) reordering of data access and index update. On ARM Cortex‑M (no cache, single core), this is sufficient; if using Cortex‑M with DMA/shared memory or multicore, stronger barriers (DMB) or atomic ops needed. Complexity & Edge Cases O(1) push/pop, uses size power-of-two. Check size validity at init (not shown). Must ensure buffer pointer lifetime > rb usage.

HardTechnical

126 practiced

Implement an ISR-safe logging mechanism that replaces printf calls in interrupts. Requirements: minimal overhead in ISR, no heap use, store textual or binary events to a fixed-size RAM circular buffer, provide a non-blocking API for ISR to append events, and a consumer in main context to flush to UART/flash. Provide C code for append() and consumer() functions and discuss crash/power-loss considerations.

Sample Answer

Approach (brief) Use a fixed-size byte circular buffer in RAM (power-of-two length). ISR does a non-blocking append of an event (header: 1-byte type + 2-byte length) using atomic index updates and a simple commit marker so a consumer can detect partial writes. Single ISR writer / single main-context reader means no mutexes; only atomic counter reads/writes and barrier semantics are required. Data structures c#include <stdint.h> #include <string.h> #define RING_SIZE 1024 // power of two typedef struct { uint8_t buf[RING_SIZE]; uint32_t mask; volatile uint32_t write; volatile uint32_t read; } ring_t; ring_t ring = {.mask = RING_SIZE-1, .write = 0, .read = 0}; ISR append (non-blocking, minimal work) c// returns 0 on success, -1 if not enough space int append(uint8_t type, const void *data, uint16_t len) { uint32_t w = ring.write; uint32_t r = ring.read; // single-reader semantics OK uint32_t free = RING_SIZE - (w - r); uint32_t total = 1 + 2 + len + 1; // type + len(2) + payload + commit if (total > free) return -1; uint32_t pos = w & ring.mask; // write header: type, len (LSB first) ring.buf[pos] = type; pos = (pos + 1) & ring.mask; ring.buf[pos] = (uint8_t)(len & 0xFF); pos = (pos + 1) & ring.mask; ring.buf[pos] = (uint8_t)((len >> 8) & 0xFF); pos = (pos + 1) & ring.mask; // write payload (may wrap) uint32_t first = RING_SIZE - pos; if (first >= len) { memcpy(&ring.buf[pos], data, len); pos = (pos + len) & ring.mask; } else { memcpy(&ring.buf[pos], data, first); memcpy(&ring.buf[0], (const uint8_t*)data + first, len - first); pos = (len - first) & ring.mask; } // commit marker: 0xA5 indicates fully written ring.buf[pos] = 0xA5; // single byte commit // publish: advance write index (atomic store) // ensure commit byte is visible before write update (compiler barrier) __asm__ volatile("" ::: "memory"); ring.write = w + total; return 0; } Consumer (main context): parse and flush to UART/flash c// process_one returns 1 if processed an event, 0 if none available int process_one(void (*flush_cb)(const uint8_t*, uint16_t)) { uint32_t r = ring.read; uint32_t w = ring.write; if (r == w) return 0; uint32_t pos = r & ring.mask; uint8_t type = ring.buf[pos]; pos = (pos + 1) & ring.mask; uint16_t len = ring.buf[pos]; pos = (pos + 1) & ring.mask; len |= ((uint16_t)ring.buf[pos]) << 8; pos = (pos + 1) & ring.mask; // ensure commit byte present at expected location uint32_t commit_pos = (r + 1 + 2 + len) & ring.mask; if (ring.buf[commit_pos] != 0xA5) { // partial/invalid - stop processing return 0; } // collect payload into a temp buffer (size bounded) static uint8_t tmp[256]; if (len > sizeof(tmp)) { // oversized, skip or truncate len = sizeof(tmp); } uint32_t first = RING_SIZE - pos; if (first >= len) { memcpy(tmp, &ring.buf[pos], len); } else { memcpy(tmp, &ring.buf[pos], first); memcpy(tmp + first, &ring.buf[0], len - first); } // call flush callback flush_cb(&type, 1); // example: send type first flush_cb(tmp, len); // send payload // advance read pointer past this record ring.read = r + 1 + 2 + len + 1; return 1; } Crash / power-loss considerations Partial writes: commit marker at end lets consumer detect incomplete entries. On boot, consumer should scan buffer from read to write and discard trailing partial event(s). Corruption: use a checksum (e.g., 8-bit CRC) instead of a single commit byte for higher fidelity. Durability: RAM alone is volatile — consider battery-backed RAM or explicitly flushing critical events to non-volatile storage (flash/FRAM) from main context. When writing to flash, use wear-leveling and atomic page writes; write-to-flash must be done outside ISR. Ordering: single-writer guarantees FIFO ordering. If multiple contexts must log, funnel through a single ISR-safe API or use lockless multi-producer algorithms with sequence reservation. Power-fail during consumer flush: ensure consumer writes an atomic footer or sequence number in persistent storage so on reboot you can detect last fully-written block. Performance notes: ISR does one bounds check, short memcpy (payload copy cost), one volatile write to publish. No heap, no blocking.

HardSystem Design

89 practiced

Design an atomic, zero-copy, high-throughput API for an application that streams sensor samples from an ISR to a processing thread using circular DMA buffers. Detail how you would coordinate buffer ownership, detect overruns, expose completed packet lengths, and allow the processor to process one buffer while DMA continues filling another.

Sample Answer

Clarify constraints & goals Zero-copy: CPU must get direct pointers into DMA memory (no memcopy). Atomic: ownership transfer must be race-free between ISR/DMA and processing thread. High-throughput: minimal ISR work, lock-free, pipeline DMA → process concurrently. Platform: circular DMA (hardware writes samples to ring buffer), CPU may have caches. High-level design Use N fixed-size buffer segments in circular DMA memory (N≥2). Each segment has a small header: seq (uint32), len (uint32), flags (enum: FREE | WRITING | READY | READING). DMA writes into segments sequentially; when finishing a segment it atomically updates len then flags=READY and increments seq. Processing thread claims READY segments by atomically swapping flags to READING, reads len and processes buffer, then sets flags=FREE. ISR only updates descriptor when DMA completes (or DMA engine raises IRQ); ISR does minimal work: mark READY and poke a queue/semaphore. Concurrency & atomicity Use 32-bit atomic stores for flags and seq; ordering enforced with memory barriers (compiler + CPU fence). Ownership transition pattern: DMA path: write data -> write len (release fence) -> store flags=READY (atomic release). Processor: atomically CAS flags from READY→READING (acquire fence) then read len and data pointer. No locks required; CAS ensures single owner. Overrun detection Maintain seq numbers per segment. When DMA is about to start writing a segment whose flags != FREE, increment an overrun counter and set an OVERRUN flag; optionally drop oldest segment (backpressure) or signal higher layer. Also track distance between DMA write index and CPU read index; if distance ≥ N => overrun. Expose completed packet lengths DMA must write len (actual bytes) before setting READY. Processor reads len after acquiring ownership. Provide accessor: (void* ptr, uint32_t len, uint32_t seq). Allow concurrent processing With N≥2, DMA writes to upcoming FREE segments while CPU processes READING segment. Use ring indices: dma_tail (where DMA writes), cpu_head (where CPU reads). DMA never writes into a segment not FREE. Cache coherency On cacheable systems, ISR/DMA path must: clean data cache lines before setting READY (DMA->memory) and processor must invalidate cache lines before reading (or use non-cacheable DMA region). Use platform cache ops around ownership transitions. Example C structs & snippets ctypedef enum { FREE=0, WRITING=1, READY=2, READING=3 } buf_state_t; typedef struct { atomic_uint32_t seq; atomic_uint32_t len; atomic_uint32_t state; uint8_t data[SEGMENT_SIZE]; } segment_t; segment_t ring[N]; atomic_uint32_t dma_idx = 0; atomic_uint32_t cpu_idx = 0; DMA completion ISR: c// ISR context: minimal segment_t *s = &ring[idx]; atomic_thread_fence_release(); atomic_store(&s->len, actual_len); atomic_store(&s->state, READY); // single atomic store for publish signal_processor(); Processor claim: cif (atomic_compare_exchange_strong(&s->state, READY, READING)) { atomic_thread_fence_acquire(); uint32_t len = atomic_load(&s->len); process(s->data, len); atomic_store(&s->state, FREE); } Trade-offs & tuning N larger → more buffering, higher latency; N small → risk overruns. Use scatter-gather DMA descriptors for variable-length packets. If strict latency, choose N=2 (double-buffer); for throughput, N≥4. For hard real-time, avoid heap; pre-allocate ring and keep ISR minimal. This design gives atomic, zero-copy ownership handoff, explicit lengths, overrun detection via seq/state, and permits DMA and processor to work concurrently.

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