Interrupts & ISR Design Questions

Approach (brief)
Implement an SPSC ring buffer with capacity N (compile-time power of two). Head is written by producer (ISR), tail by consumer (task). Use C11 atomics for safe cross-context synchronization: producer does an atomic load/acquire of tail and atomic store/release of head; consumer does the mirrored ordering. This is non-blocking and lock-free for SPSC.

Code

#include <stdatomic.h>
#include <stdint.h>
#include <stdbool.h>

#define CAPACITY  8U               /* must be power of two */
_Static_assert((CAPACITY & (CAPACITY - 1)) == 0, "CAPACITY must be power of two");

typedef struct {
    void *buf[CAPACITY];
    atomic_uint_fast32_t head;     /* index written by producer (ISR) */
    atomic_uint_fast32_t tail;     /* index written by consumer (task) */
} spsc_ring_t;

/* Called from ISR context. Returns true on success, false if full. */
bool enqueue_isr(spsc_ring_t *r, void *item) {
    uint32_t head = atomic_load_explicit(&r->head, memory_order_relaxed);
    uint32_t tail = atomic_load_explicit(&r->tail, memory_order_acquire); /* see ordering */
    uint32_t next = (head + 1) & (CAPACITY - 1);

    if (next == tail) return false; /* full */

    r->buf[head] = item;
    /* publish new head so consumer sees the write to buf[head] */
    atomic_store_explicit(&r->head, next, memory_order_release);
    return true;
}

/* Called from task context. Returns true and sets *out on success, false if empty. */
bool dequeue_task(spsc_ring_t *r, void **out) {
    uint32_t tail = atomic_load_explicit(&r->tail, memory_order_relaxed);
    uint32_t head = atomic_load_explicit(&r->head, memory_order_acquire);

    if (tail == head) return false; /* empty */

    *out = r->buf[tail];
    uint32_t next = (tail + 1) & (CAPACITY - 1);
    atomic_store_explicit(&r->tail, next, memory_order_release);
    return true;
}

Ordering guarantees / reasoning

• Producer (ISR): writes buf[head] then does atomic store(head, release). Release ensures the store to the buffer is visible before head update; consumer acquiring head will see the buffer write.
• Consumer (task): atomic load(head, acquire) before reading buf slot ensures it sees a fully-published item. After consuming, it store(tail, release) so producer's load(tail, acquire) sees the latest tail.
• Using memory_order_relaxed for index loads you own is OK. Acquire/Release pair provides necessary cross-context synchronization.
• Volatile alternative: on many MCUs a pair of volatile reads/writes with explicit compiler barriers (and ensuring single-writer single-reader) can work, but C11 atomics express intent and portability; prefer atomics for correctness across compilers/optimizers.

Notes

• No dynamic allocation, O(1) operations, ISR-safe (no blocking, no malloc, no syscalls).
• Ensure CAPACITY > 1. If ISR priority and memory model are unusual, validate with target toolchain/arch.

Approach overview
Describe which wake sources are allowed by the MCU, filter/debounce the GPIO to avoid spurious wakes, and trade off wake latency vs average current by choosing clock sources, debounce time, and whether to sample in deep sleep or light sleep.

Which interrupts can wake from deep sleep

• RTC alarm (dedicated low-power RTC interrupt) — reliable, low current.
• External GPIO with wake-on-edge (pin-muxed to event/EXTI line) — common on MCU families.
• Low-power comparator/analog watchdog (if supported) — for threshold wakes.
• Dedicated low-power peripherals (touch, BLE radio) if hardware supports retention wake.
  Confirm on target MCU which interrupts are routed to the deep-sleep wake vector.

Debounce & filtering to minimize false wakes

• Hardware first: use Schmitt-input GPIO, series resistor + capacitor (RC filter) to ground, or low-pass followed by Schmitt trigger. Recommended RC: R=10k, C=100nF gives 1 ms corner.
• Software on wake: on external wake, on boot/ISR sample line and timestamp; if level unstable, sleep briefly (ms) and re-check. Keep software debounce short to avoid long wake current.
• Use edge detection only on the required direction; mask opposite edges. If contact bounce creates many edges, configure the wake to a level and use RTC to confirm stable level after debounce window.

Minimize false wakes due to noise

• Add hysteresis (Schmitt) and shielding. Use pull-ups/downs sized to survive EMI but limit current (e.g., 100k for low leakage).
• Use comparator with integrated debounce or window detection.
• Route noisy signals through a GPIO expander with integrated debounce or interrupt aggregation.
• Use wake-source validation in boot: if spurious, immediately go back to sleep (early return path before enabling heavy peripherals).

Balance wake latency vs power

• Longer debounce/time-to-validate reduces false wakes but increases latency and active energy per event. Choose debounce T such that (false wake rate * E_wake) << (legitimate wake rate * acceptable latency cost).
• Use low-frequency oscillator (e.g., 32.768 kHz) for RTC to allow low-power retention and sub-second alarms; if sub-10 ms latency is required, keep a faster low-power clock or use a wake-on-edge GPIO with minimal debounce.
• Use two-stage wake: deep sleep -> quick ISR validates signal and, if likely valid, switch to full clock and resume. If false, go back to sleep quickly.
• Example heuristic: for human input buttons use 5–20 ms debounce; for pulse sensors use hardware filtering and shorter debounce (<2 ms).

Example minimal ISR / debounce pattern

// In deep-sleep EXTI handler (very short)
void EXTI_handler(void) {
    // disable further EXTI to avoid re-entry
    EXTI_DisableLine(LINE);
    // record timestamp (low-res)
    wake_timestamp = rtc_read_ms();
    // request light sleep -> run small validation task after wake
    request_wake_to_run_validation();
}

// Validation after clocks enabled
bool validate_wake(void) {
    delay_ms(5); // short debounce tuned for source
    if (gpio_read(INPUT_PIN) == EXPECTED_LEVEL) return true;
    // false wake: re-enable EXTI and go back to deep sleep
    EXTI_EnableLine(LINE);
    enter_deep_sleep();
    return false;
}

Key trade-offs (summary)

• Hardware filtering + Schmitt: increases BOM but best for noise.
• Software debounce: flexible, no extra hardware, but costs wake energy.
• Short latency requires tolerating some false wakes or using hardware comparator + fast validation.
  Pick parameters based on measured false-wake rate, wake energy, and required responsiveness.

Clarify goals & constraints

• Balance interrupt load across N cores while guaranteeing low latency for real-time (RT) tasks.
• HW: multi-core SoC with GIC-like distributor/redistributor, DMA engines, coherent interconnect supporting cache-coherency (or not).
• SW: RT threads pinned to cores, per-core ISR stacks, limited memory.

Routing strategies

• Affinity (static): assign interrupts to cores based on device class and RT requirements. Example: assign high-priority sensor IRQs to core 0 (RT), less-critical network IRQs round-robin across cores 1..N-1. Simple, predictable latency.
• Dynamic steering: use a mid-layer interrupt router (kernel driver or GIC ITS) to migrate IRQ affinity at runtime based on per-core load counters and CPU utilization. On spike, steer less-critical IRQs away from overloaded or RT cores.
• Hybrid: static affinity for RT/latency-sensitive IRQs; dynamic steering for best-effort IRQs.

Implementation details

• Use per-IRQ priority and target list in the GIC. For dynamic steering, maintain a bitmap of eligible cores and update target registers atomically.
• Implement hysteresis and rate-limiting to avoid ping-ponging.

Cache-coherency implications

• If data touched by ISR is cached in the target core, route IRQ to that core to avoid cache misses and data bounce.
• For non-coherent peripherals or DMA, explicitly perform cache maintenance (invalidate before use, clean after DMA completes). Prefer steering DMA completions to the core that owns the buffer to maintain cache locality.
• If system supports IPI-based processing: keep ISR minimal (ack + schedule DPC/tasklet) to let worker on owning core handle heavy data with correct cache state.

Per-core ISR stacks & latency

• Allocate per-core ISR stacks in tightly-coupled SRAM or reserved kernel stacks to avoid stack switching and reduce latency.
• Keep top-half fast: acknowledge and mask in ISR, defer processing to per-core bottom-half or RT thread.
• Pin RT threads and ISRs on same core where required; raise IRQ thread priority if using threaded IRQs.

DMA and interrupt affinity interaction

• Prefer DMA engines to write to memory regions owned by a specific core to preserve cache locality; program DMA channel affinity when possible.
• On DMA completion IRQ: route to core owning buffer; if IRQ lands elsewhere, either do cache maintenance and hand off work via lockless queue to owner core, or use IPI to notify owner—trade-off: extra latency vs. cache efficiency.
• If hardware supports MSI/MSI-X per DMA channel, bind vector to desired core.

Trade-offs

• Static affinity => predictable latency but less balanced load.
• Dynamic steering => better throughput, adds complexity and potential jitter; mitigate with policies and cache-awareness.

Result: predictable low-latency for RT tasks by pinning and affinity, while leveraging dynamic steering for background IRQs and carefully coordinating DMA + cache maintenance to avoid extra latency from cache misses.

Approach (brief)
Provide a minimal, non-blocking ISR that clears the peripheral interrupt flag, avoids heap or blocking calls, and signals the application either via a volatile lock-free flag or via FreeRTOS task notification.

Code (STM32-style register names as example)

#include <stdint.h>
#include "FreeRTOS.h"
#include "task.h"

/* Lock-free flag option */
volatile uint32_t gpio_event_flag = 0;

/* FreeRTOS task handle to notify (set by main) */
TaskHandle_t gpioTaskHandle = NULL;

/* ISR for GPIO pin 0 (example). CMSIS name used by startup vector table. */
void EXTI0_IRQHandler(void)
{
    /* 1) Clear hardware interrupt flag (write 1 to pending bit) */
    EXTI->PR = (1U << 0); /* platform-specific: clear pending for line 0 */

    /* 2a) Simple lock-free flag (no blocking, no heap) */
    gpio_event_flag = 1;

    /* 2b) OR: notify a FreeRTOS task from ISR (non-blocking) */
    BaseType_t xHigherPriorityTaskWoken = pdFALSE;
    if (gpioTaskHandle != NULL) {
        vTaskNotifyGiveFromISR(gpioTaskHandle, &xHigherPriorityTaskWoken);
        portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
    }
}

Notes:

• Use the correct peripheral register to clear the interrupt for your MCU (some require writing 1, others clearing bits).
• gpio_event_flag must be volatile to prevent compiler optimizations.
• vTaskNotifyGiveFromISR and portYIELD_FROM_ISR are ISR-safe and do not allocate heap.
• Do not call blocking APIs, printf, malloc, or mutexes inside ISR.

Approach (brief)
Use a fixed-size byte circular buffer in RAM (power-of-two length). ISR does a non-blocking append of an event (header: 1-byte type + 2-byte length) using atomic index updates and a simple commit marker so a consumer can detect partial writes. Single ISR writer / single main-context reader means no mutexes; only atomic counter reads/writes and barrier semantics are required.

Data structures

#include <stdint.h>
#include <string.h>
#define RING_SIZE 1024  // power of two
typedef struct { uint8_t buf[RING_SIZE]; uint32_t mask; volatile uint32_t write; volatile uint32_t read; } ring_t;
ring_t ring = {.mask = RING_SIZE-1, .write = 0, .read = 0};

ISR append (non-blocking, minimal work)

// returns 0 on success, -1 if not enough space
int append(uint8_t type, const void *data, uint16_t len) {
    uint32_t w = ring.write;
    uint32_t r = ring.read; // single-reader semantics OK
    uint32_t free = RING_SIZE - (w - r);
    uint32_t total = 1 + 2 + len + 1; // type + len(2) + payload + commit
    if (total > free) return -1;

    uint32_t pos = w & ring.mask;
    // write header: type, len (LSB first)
    ring.buf[pos] = type; pos = (pos + 1) & ring.mask;
    ring.buf[pos] = (uint8_t)(len & 0xFF); pos = (pos + 1) & ring.mask;
    ring.buf[pos] = (uint8_t)((len >> 8) & 0xFF); pos = (pos + 1) & ring.mask;
    // write payload (may wrap)
    uint32_t first = RING_SIZE - pos;
    if (first >= len) {
        memcpy(&ring.buf[pos], data, len);
        pos = (pos + len) & ring.mask;
    } else {
        memcpy(&ring.buf[pos], data, first);
        memcpy(&ring.buf[0], (const uint8_t*)data + first, len - first);
        pos = (len - first) & ring.mask;
    }
    // commit marker: 0xA5 indicates fully written
    ring.buf[pos] = 0xA5; // single byte commit
    // publish: advance write index (atomic store)
    // ensure commit byte is visible before write update (compiler barrier)
    __asm__ volatile("" ::: "memory");
    ring.write = w + total;
    return 0;
}

Consumer (main context): parse and flush to UART/flash

// process_one returns 1 if processed an event, 0 if none available
int process_one(void (*flush_cb)(const uint8_t*, uint16_t)) {
    uint32_t r = ring.read;
    uint32_t w = ring.write;
    if (r == w) return 0;
    uint32_t pos = r & ring.mask;
    uint8_t type = ring.buf[pos]; pos = (pos + 1) & ring.mask;
    uint16_t len = ring.buf[pos]; pos = (pos + 1) & ring.mask;
    len |= ((uint16_t)ring.buf[pos]) << 8; pos = (pos + 1) & ring.mask;
    // ensure commit byte present at expected location
    uint32_t commit_pos = (r + 1 + 2 + len) & ring.mask;
    if (ring.buf[commit_pos] != 0xA5) {
        // partial/invalid - stop processing
        return 0;
    }
    // collect payload into a temp buffer (size bounded)
    static uint8_t tmp[256];
    if (len > sizeof(tmp)) { // oversized, skip or truncate
        len = sizeof(tmp);
    }
    uint32_t first = RING_SIZE - pos;
    if (first >= len) {
        memcpy(tmp, &ring.buf[pos], len);
    } else {
        memcpy(tmp, &ring.buf[pos], first);
        memcpy(tmp + first, &ring.buf[0], len - first);
    }
    // call flush callback
    flush_cb(&type, 1);       // example: send type first
    flush_cb(tmp, len);       // send payload
    // advance read pointer past this record
    ring.read = r + 1 + 2 + len + 1;
    return 1;
}

Crash / power-loss considerations

• Partial writes: commit marker at end lets consumer detect incomplete entries. On boot, consumer should scan buffer from read to write and discard trailing partial event(s).
• Corruption: use a checksum (e.g., 8-bit CRC) instead of a single commit byte for higher fidelity.
• Durability: RAM alone is volatile — consider battery-backed RAM or explicitly flushing critical events to non-volatile storage (flash/FRAM) from main context. When writing to flash, use wear-leveling and atomic page writes; write-to-flash must be done outside ISR.
• Ordering: single-writer guarantees FIFO ordering. If multiple contexts must log, funnel through a single ISR-safe API or use lockless multi-producer algorithms with sequence reservation.
• Power-fail during consumer flush: ensure consumer writes an atomic footer or sequence number in persistent storage so on reboot you can detect last fully-written block.

Performance notes: ISR does one bounds check, short memcpy (payload copy cost), one volatile write to publish. No heap, no blocking.