Low-Power Design and Power Management Questions

Approach: I’ll list each measurement method, then give strengths and limitations focused on resolution, dynamic range, sampling rate, and intrusiveness — from the viewpoint of an embedded developer measuring MCU/IoT power.

Handheld DMM

• Strengths: Simple, cheap, good DC accuracy for steady-state current. Resolution ~µA–mA depending on meter; dynamic range wide (µA–A).
• Limitations: Low sampling rate (1–10 samples/s), cannot capture transients; typically intrusive if you must break the power path; burden on low-voltage rails can alter results.

Oscilloscope + Current Probe (clamp or Hall)

• Strengths: High bandwidth (MHz), excellent for capturing fast transients and duty-cycle behavior; non-invasive clamp probes avoid circuit modification.
• Limitations: Resolution limited for low currents (noise floor ~mA for many probes); dynamic range moderate; probes can be expensive; Hall/clamp probes may be bulky and less accurate for µA-level.

Shunt Resistor + Amplifier + ADC

• Strengths: Very flexible: choose shunt + op-amp gain and ADC to get µA resolution, wide dynamic range with selectable gain; sampling rate depends on ADC (kHz–MHz).
• Limitations: Intrusive (adds series resistance and voltage drop), needs careful layout to avoid noise; amplifier offset and ADC quantization set lower limit.

Monsoon Power Monitor / TI EnergyTrace / Nordic Power Profiler

• Strengths: Purpose-built for low-power devices: high resolution (nA–µA), programmable sampling (kHz), integrated current sourcing/sinking, convenient logging and energy calculation.
• Limitations: Costly, limited maximum voltage/current ranges, may be slightly intrusive (replace battery/power rail), and high-speed transients above device spec may be missed depending on model.

uCurrent (precision low-current adapter)

• Strengths: Very low burden and high sensitivity for µA–mA ranges, simple and inexpensive.
• Limitations: Lower sampling rate (meant for DMM readout), not suited to fast transients, limited dynamic range (best for small currents).

Summary tips for interviews

• Choose tool by trade-offs: need transient capture → scope; need absolute energy over long run → Monsoon/Power Profiler; best custom sensitivity/control → shunt+amp+ADC. Always mention burden, bandwidth, and noise floor when justifying choices.

Situation & goal
I need to minimize average energy per sensor report on a BLE node while keeping responsiveness (max report latency) acceptable. Key levers: connection interval & slave latency, advertising params, packet aggregation (GATT/ATT/notifications), radio duty cycling, and DVFS for MCU and radio blocks.

Interaction summary

• Longer connection intervals + higher slave latency reduce radio wakeups but increase worst-case latency.
• Advertising interval affects discovery/unsolicited reporting energy vs. discovery latency.
• Aggregating sensor samples into single BLE notifications amortizes radio/stack overhead but increases per-report latency.
• Aggressive radio duty cycling must be synchronized with connection windows and IRQ handling.
• DVFS: lower CPU/Vcore between radio events; scale up shortly before radio window and sensor sampling.

Concrete firmware changes

• Use connection-oriented operation where possible. Set base connection_interval = 50–200 ms and slave_latency = 0–4 depending on acceptable latency; tune to keep effective avg latency ≤ target.
• Implement sample buffering with a configurable aggregation window (e.g., buffer up to N samples or T ms — N=8 or T=200 ms). Send a single GATT notification with compressed payload.
• Align sampling timers to connection event timing (read connection event time from controller) so MCU wakes once to sample+serialize+TX.
• Implement precise radio pre-wake: schedule DVFS upshift and peripheral enable ~2–5 ms before radio start using a hardware timer to allow regulator/stabilization.
• After TX/RX complete, drop to low-power mode and scale CPU down immediately; use tickless RTOS or WFI to avoid periodic wakeups.
• Add adaptive policy: if queue grows or latency budget nears, reduce aggregation window and shorten connection interval dynamically.

DVFS coordination strategy

• State machine: IDLE (lowest freq) → PREP (boost to medium freq, enable ADC/GPIO) at T_prep before event → RADIO (max allowed freq during serialization + HCI interaction) → POST (brief tail time) → IDLE.
• Calibrate T_prep per hardware (measure regulator settle + PLL lock).
• Use performance counters to measure energy per report and latency; run online optimizer to adjust conn interval, slave latency, and aggregation window to minimize energy under latency SLA.

Metrics & edge cases

• Measure average energy/report, 95th percentile latency, and packet error retransmit rate.
• Edge cases: connection loss (fall back to advertising), urgent event override (send immediately with reduced aggregation), and variable RSSI causing retransmits — adapt MI/TX power or reduce aggregation if retransmits spike.

This approach reduces wakeups, amortizes protocol overhead, and ensures DVFS transitions are timed to avoid wasted energy while holding responsiveness within SLA.

Approach & assumptions

• Compute average current from sleep/active duty cycle.
• Assume ideal battery (no self-discharge), regulator losses ignored, capacity available over operating range, and duty cycle is steady over life.

Calculation

• Sleep current = 5 μA for 99% → 0.99 × 5 μA = 4.95 μA

• Active current = 15 mA for 1% → 0.01 × 15,000 μA = 150 μA

• Average current = 4.95 μA + 150 μA = 154.95 μA ≈ 155 μA = 0.155 mA

• Battery capacity = 2000 mAh

• Life (hours) = 2000 mAh / 0.155 mA ≈ 12,903 hours

• Life (days) = 12,903 / 24 ≈ 538 days ≈ 1.47 years

Notes / practical caveats

• Real-life will be lower due to regulator inefficiency, self-discharge, temperature effects, and reduced usable capacity near cutoff.
• Example: with 90% power conversion efficiency, effective current = 0.155 / 0.9 ≈ 0.172 mA → ~480 days.

Approach (brief)
Use a low-power timer as the ADC trigger (TRGO), ADC in hardware-trigger + DMA mode, DMA circular into a double-buffer (N samples * 2), and enable DMA Half-Transfer (HT) and Transfer-Complete (TC) interrupts. Put CPU to sleep (WFI). DMA HT/TC interrupts are configured to wake the CPU; handler processes the ready half and returns to sleep.

Configuration steps (pseudocode C)

// Buffer: two halves of size HALF
#define HALF 128
uint16_t adc_buf[2 * HALF];

// 1) Timer: periodic trigger (low-power)
void timer_init() {
  TIMER->PSC = prescaler;
  TIMER->ARR = period_ticks;        // sample rate
  TIMER->CR2 = TRGO_ON_UPDATE;      // make update event generate TRGO
  TIMER->CR1 |= TIMER_ENABLE_LOWPOWER; // enable in low-power mode if supported
  TIMER->CR1 |= TIMER_ENABLE;
}

// 2) ADC: external trigger, DMA enabled
void adc_init() {
  ADC->CR2 = ADC_ENABLE;
  ADC->SMPR = sampling_time;
  ADC->SQR = channel_config;
  ADC->CR2 |= ADC_EXT_TRIG;         // enable external trigger (from TIMER TRGO)
  ADC->CR2 |= ADC_DMA_ENABLE;       // enable DMA requests
  ADC->CR2 |= ADC_CONTINUOUS_DISABLE; // rely on timer trigger
}

// 3) DMA: circular, peripheral=ADC_DR, mem=adc_buf
void dma_init() {
  DMA->CCR = 0;
  DMA->CPAR = (uint32_t)&ADC->DR;
  DMA->CMAR = (uint32_t)adc_buf;
  DMA->CNDTR = 2 * HALF;
  DMA->CCR |= MEM_INC | PERIPH_SIZE_HALFWORD | MEM_SIZE_HALFWORD | CIRCULAR;
  DMA->CCR |= HTIE | TCIE;          // enable Half-Transfer & Transfer-Complete interrupts
  NVIC_EnableIRQ(DMA_IRQn);         // ensure NVIC allows wake from sleep
  DMA->CCR |= ENABLE;
}

// 4) Power: enable deep sleep and allow DMA/IRQ to wake CPU
void power_init_and_sleep() {
  // configure sleep mode (STOP or SLEEP) per MCU
  while (1) {
    __WFI(); // wait for interrupt; DMA HT/TC wakes CPU because IRQ pending
  }
}

// 5) DMA IRQ Handler: process half-buffers and clear flags
void DMA_IRQHandler(void) {
  if (DMA->ISR & HT_FLAG) {
    DMA->IFCR = HT_CLEAR;
    process_buffer(adc_buf, HALF);    // process first half [0..HALF-1]
  }
  if (DMA->ISR & TC_FLAG) {
    DMA->IFCR = TC_CLEAR;
    process_buffer(adc_buf + HALF, HALF); // process second half
  }
  // return: CPU can go back to sleep
}

Which interrupts should wake the CPU

• DMA Half-Transfer interrupt (HT) — wakes CPU to process first half.
• DMA Transfer-Complete interrupt (TC) — wakes CPU to process second half.
  (Do NOT rely on ADC EOC interrupts when using DMA; use DMA HT/TC.)

Notes, reasoning & best practices

• Timer TRGO ensures ADC samples happen while CPU sleeps.
• DMA circular avoids re-arming; HT/TC split enables low-latency processing without data loss.
• Ensure NVIC priority and wake capability: mark DMA IRQ as wake source and set appropriate interrupt priority.
• Keep handler short: schedule work or process small batches; if heavy processing required, set a flag and do work at lower priority or in a task context.
• Careful with cache/coherency on MCUs with D-cache: use non-cached buffers or perform cache maintenance around DMA memory.

Situation & goal
Design a thermal-aware DVFS controller running on an SoC MCU that reads on-die sensors and throttles CPU/GPU frequencies to keep T <= T_target while minimizing performance loss.

Control-loop design

• Use a PID + hysteresis hybrid:
  • PID computes continuous thermal control effort (delta_power) every control interval (e.g., 100–500 ms).
  • Hysteresis on frequency step decisions to avoid flipping between adjacent P-states.
• Tune conservatively: small Ki to avoid integral wind-up; use conditional integration when actuator saturated.

Sensor noise & filtering

• Apply a short median filter then a low-pass IIR:

// simple IIR: y[n] = a*y[n-1] + (1-a)*x[n]
float filter(float x){ y = a*y + (1-a)*x; return y; }

• Optional Kalman for multi-sensor fusion (redundant sensors).
• Estimate sensor latency and bias; compensate in control law.

Stability & anti-oscillation

• Enforce min dwell time per DVFS step (e.g., 500–2000 ms).
• Rate-limit frequency changes and use step-size caps (no >2 steps per change).
• Anti-windup: clamp integrator when output limited.
• Add feedforward: map workload metrics (util %, IPC) to predicted thermal rise to preempt overshoot.
• When rapid temp spike, use fast emergency throttle path with longer cooldown before restoring.

Example decision policy

• If filtered_T > T_target + H => force down by N steps.
• Else if PID_output suggests lower freq and temp < T_target - H and min_dwell passed => step up.

Metrics & testing

• Validate with thermal profiles, step-input workload, and randomized workloads.
• Metrics: time above T_target, average performance loss, oscillation frequency, energy consumption.

This approach balances responsiveness and stability for embedded SoC constraints.