Algorithmic Complexity & Code-Level Optimization Questions

Reasoning about the time and space complexity of code and applying local optimizations that materially change performance. Covers Big-O analysis and performance modeling, data-structure selection, hot-loop and allocation reduction, and knowing when an algorithmic change beats micro-optimization. Emphasizes performance-aware coding grounded in complexity rather than premature tuning.

MediumTechnical

103 practiced

An algorithm runs in O(n * sqrt(n)) time but must scale to n up to 1e8. Propose practical algorithmic and engineering strategies to make this feasible: consider approximation, sampling, divide-and-conquer, precomputation, parallelization, and hardware acceleration. For each strategy provide expected asymptotic or constant-factor improvements and discuss tradeoffs in memory, accuracy, and implementation complexity.

Sample Answer

Situation: You have an O(n * sqrt(n)) algorithm and must handle n up to 1e8 — direct execution is infeasible (n*sqrt(n) ~ 1e12 operations). Below are practical strategies (algorithmic + engineering), expected improvements, and tradeoffs tailored to an ML engineering setting.

1) Approximation / Relaxed problem- Idea: Replace exact computation with approximate algorithms (sketches, locality-sensitive hashing, quantization, pruning).- Improvement: Often reduces to O(n) or O(n log n) with small constant factors (e.g., LSH for nearest neighbors ~ O(n^(1+ρ)) but practical near-linear).- Tradeoffs: Loss of exactness/recall; needs eval of accuracy vs business metric. Low memory if using compact sketches.

2) Sampling / Subsampling- Idea: Work on a representative sample (stratified or importance sampling) and extrapolate.- Improvement: Cost proportional to sample size m: O(m * sqrt(m)) with m << n — effectively constant-factor or orders-of-magnitude reduction.- Tradeoffs: Statistical variance / bias; requires careful sampling design and confidence bounds. Memory low; simple to implement.

3) Divide-and-conquer / Blocking- Idea: Partition data into blocks processed independently with merge/aggregation (external memory if needed).- Improvement: Reduces per-step working set and enables streaming; asymptotic unchanged but enables processing that fits cache/IO and parallelism.- Tradeoffs: Merge cost and boundary effects; needs IO-aware design; moderate complexity.

4) Precomputation / Indexing- Idea: Precompute auxiliary structures (indices, sorted lists, cumulative stats) so heavy work per query is reduced.- Improvement: Amortizes cost: preprocessing O(n log n) or O(n) then per-query O(log n) or O(1). For batch tasks, total cost can drop from O(n sqrt(n)) to near-linear plus cheap queries.- Tradeoffs: Extra memory for indices; upfront compute time; maintenance complexity for dynamic data.

5) Parallelization (multi-core / distributed)- Idea: Parallelize across cores or cluster — split n into p parts, run in parallel.- Improvement: Ideal speedup ~1/p (wall-clock down to O((n*sqrt(n))/p)); practically limited by Amdahl’s law and synchronization/IO.- Tradeoffs: Implementation complexity (distributed frameworks, fault tolerance), network overhead, increased memory footprint.

6) Hardware acceleration (GPU / TPU / FPGA)- Idea: Map computation to massively parallel hardware (vectorize, batch operations).- Improvement: Large constant-factor speedups (10x–100x) for data-parallel kernels; if algorithm vectorizable, throughput improves dramatically while asymptotic stays same.- Tradeoffs: Requires algorithm refactor, memory transfer overhead, limited by memory size of accelerator.

Combined strategy (recommended for ML engineer):- First, ask if exactness is required; if not, use approximation + sampling to reduce n to m.- Precompute indexes or sketches to amortize work.- Implement divide-and-conquer to stream blocks that fit GPU/CPU caches and parallelize across nodes.- Offload heavy inner loops to GPU/TPU for constant-factor speedups.- Validate accuracy via holdout and statistical bounds, monitor drift, and add fallback for critical cases.

Summary of impacts:- Asymptotic reductions: approximation/sampling can move from O(n sqrt(n)) toward O(n) or O(n log n) empirically.- Constant-factor reductions: hardware + parallelism can yield 10–100x speedups.- Tradeoffs: accuracy vs speed, more memory for indices/accelerators, and higher implementation/operational complexity. Choose a mix based on SLAs, acceptable error, and available infra.

MediumTechnical

95 practiced

Discuss performance and numerical stability trade-offs between float32, float16, and bfloat16 for training and inference. Explain how hardware (e.g., NVIDIA Tensor Cores, TPUs) changes these trade-offs and when mixed-precision training is safe or risky for model convergence and final accuracy.

Sample Answer

Float formats trade off dynamic range, precision (mantissa), and throughput. Key points:

- float32 (FP32): 23-bit mantissa, 8-bit exponent — highest precision and range; robust for training, slower and larger memory/bandwidth.- float16 (FP16 / IEEE half): 10-bit mantissa, 5-bit exponent — much lower precision and much smaller exponent range → risk of overflow/underflow and loss of small-gradient signal. Excellent memory and FLOPS savings on hardware that accelerates FP16 (e.g., NVIDIA Tensor Cores), but requires software mitigations for stability.- bfloat16 (BF16): 7-bit mantissa, 8-bit exponent (same exponent as FP32) — similar dynamic range to FP32 but lower precision. Keeps scale behavior (avoids overflow/underflow that plagues FP16) while still halving memory and improving throughput on hardware that supports it (TPUs, newer NVIDIA GPUs).

Hardware effects:- NVIDIA Tensor Cores (Volta/Turing/Ampere): provide large speedups for FP16 matrix ops; Ampere+ also support BF16 native ops. On these GPUs, mixed-precision FP16 yields large training speedups and memory reduction, but you must manage numerical issues (loss scaling, FP32 master weights).- TPUs: natively accelerate BF16 and typically accumulate in FP32; BF16 on TPU is often the safest reduced-precision choice because the exponent matches FP32, so many models train with little/no changes.- Older GPUs without Tensor Cores see limited benefit; quantization then is less useful.

When mixed-precision is safe:- CNNs and transformer-style architectures often train stably with mixed precision when you use: - FP32 master weights (store and update weights in FP32; cast to low precision for forward/backward), - Dynamic loss scaling (for FP16) to avoid underflow of gradients, - Accumulate reductions in FP32 (or device-accumulation that preserves range).- BF16 on TPUs or Ampere GPUs often requires fewer changes: many models converge without loss in final accuracy.

When risky / needs care:- FP16 is risky for models producing very small gradients, extremely deep/residual-less nets, RNNs/LSTMs, or training with very small batch sizes/very small learning rates — gradients can underflow; optimizers (Adam with small epsilon) and operations like layer-norm/softmax can lose precision.- Mixed precision can hurt final accuracy if scale-sensitive layers (batch norm statistics, embedding lookups) are naively cast. Also distributed training with gradient compression requires careful scaling.- Optimizers: keep optimizer state (moments) in FP32; for Adam, mantissa loss in FP16 leads to poor momentum estimates.

Practical recommendations:- Use BF16 if hardware supports it (TPU, Ampere) — best stability/perf trade-off.- If using FP16 on GPUs: use FP32 master copy of weights, dynamic loss scaling, keep batch-norm, layer-norm, embeddings, and layer outputs in FP32 where needed, and test with a small run to verify no divergence.- Monitor gradient magnitudes, loss jumps/NaNs, and final validation metrics; if instability occurs, increase precision for problematic layers or switch to BF16/FP32.- For inference, use FP16 or BF16 aggressively for speed/memory, but validate any accuracy drop (calibration, quantization-aware finetuning if necessary).

Summary: BF16 gives better numeric stability with similar memory/throughput benefits where supported. FP16 gives the biggest hardware speedups on many NVIDIA GPUs but requires loss scaling and FP32 master weights to be safe. Mixed precision is standard practice for large models, but validate per-model and keep critical accumulations/optimizer state in FP32.

MediumTechnical

94 practiced

Design an efficient streaming algorithm to approximate p50, p95, and p99 latencies for an online service handling ~10M events per day. Explain why you would pick t-digest, HDRHistogram, or the P^2 algorithm. Provide pseudocode for updating and querying your chosen data structure and analyze time and space complexity.

Sample Answer

For ~10M events/day (≈115/s) we want a single-pass, low-memory, mergeable quantile sketch. I’d pick t‑digest for latency quantiles (p50, p95, p99) because:- It provides high accuracy in tails (important for p95/p99).- It’s mergeable (useful across shards/instances).- Small memory footprint and low per-update cost.HDRHistogram is great if latencies are positive integers and you want fixed relative precision across a wide range; it uses more memory for high dynamic range but gives deterministic error bounds. P² is very lightweight but less accurate, not mergeable and poor tail accuracy — not ideal for p99 at scale.

Approach: maintain a t-digest per process, merge periodically to global digest for queries.

Pseudocode (simplified):

python

# pseudocode using t-digest API
class TDigestSketch:
    def __init__(self, delta=0.01):
        self.td = TDigest(delta=delta)  # library implementation

    def update(self, value):
        # O(log k) amortized: add a sample to nearest centroid and possibly compress
        self.td.update(value)

    def merge(self, other_td):
        # merge another tdigest (O(k) where k = centroids)
        self.td.merge(other_td.td)

    def query(self, q):
        # O(log k) amortized: estimate quantile q in [0,1]
        return self.td.quantile(q)

# usage
local = TDigestSketch()
for latency in stream:
    local.update(latency)
# periodically push local.td to aggregator which merges them and answers p50/p95/p99

Key points & complexity:- Update: amortized O(log k) where k = #centroids (typically few hundreds). Space: O(k).- Query: O(log k) to compute quantile.- Merge: O(k) to combine centroid lists.- Memory: single digest ≈ O(100–1000) centroids → kilobytes per instance.- Accuracy: configurable via compression parameter (delta); smaller delta → more centroids and better tail accuracy.

Edge cases:- Bursty traffic: compress more frequently.- Very skewed or multi-modal latencies: increase compression parameter.- If strict deterministic error bounds required and integer bins acceptable → consider HDRHistogram.

Trade-offs summary:- t‑digest: best tail accuracy + mergeability; recommended for this use case.- HDRHistogram: deterministic bucketed errors, good for integer latencies and histograms.- P²: minimal memory but worse tail accuracy and not mergeable — only for very constrained environments.

EasyTechnical

84 practiced

Estimate the RAM required to load a dataset of 12,000,000 samples where each sample has 300 float32 features and a 1-byte label. Show the raw data calculation and then include commonly overlooked overheads: numpy array metadata, Python object overhead if stored as a list of lists, and additional memory needed during training for Adam optimizer (assume Adam keeps two additional float32 tensors per parameter).

EasyTechnical

95 practiced

You need to estimate where time is spent during a single-node PyTorch training job: CPU preprocessing, GPU kernel execution, and PCIe transfers. Describe the minimal set of measurements and tools you would use to measure CPU vs GPU time and memory utilization. Explain concrete steps to distinguish a data-loading bottleneck from a compute or PCIe transfer bottleneck.

Sample Answer

Measure three things per batch: total wall-clock batch time, CPU preprocessing time, and GPU work/transfer time — plus GPU memory/utilization. Tools: Python timers + torch.cuda.Event, PyTorch Profiler (or NVIDIA Nsight Systems), and nvidia-smi for utilization/memory.

Concrete minimal measurements and how to collect them:- CPU preprocessing (data loading + transform): measure with time.time() around DataLoader iteration on host.- GPU kernel and transfer times: use torch.cuda.Event for precise GPU timings (records kernel/transfer time on device).- GPU utilization & memory: nvidia-smi --query-gpu=utilization.gpu,memory.used --format=csv -l 1 or nsys profile for detailed view.Sample timing snippet:

python

import time, torch
start_cpu = time.time()
batch = next(loader_iter)           # CPU work (decode/transform)
cpu_done = time.time()

torch.cuda.synchronize()
s0 = torch.cuda.Event(enable_timing=True); s1 = torch.cuda.Event(enable_timing=True)
s0.record()
out = model(batch.cuda(non_blocking=True))
loss = loss_fn(out, target.cuda(non_blocking=True))
loss.backward()
optimizer.step()
s1.record()
torch.cuda.synchronize()
gpu_ms = s0.elapsed_time(s1)
cpu_ms = (cpu_done - start_cpu) * 1000

How to distinguish bottlenecks:- Data-loading bound: CPU_ms ≈ total batch time and GPU utilization low/idle; increasing num_workers/prefetch/pin_memory reduces batch time.- Compute-bound: GPU_ms dominates, GPU utilization near max (nvidia-smi ~90-100%), memcpy times small relative to kernel time.- PCIe-bound: Significant time spent in transfers: large gap between CPU_done and s0 (or measure explicit cudaMemcpy timings via profiler), GPU kernels idle waiting for data, and nsys shows long cudaMemcpy / memcpy times. Reducing batch-size per transfer or enabling pinned memory and overlap (non_blocking=True + sufficient prefetch) will help.

Use PyTorch Profiler or Nsight Systems to confirm: look at timeline for memcpy vs kernel execution and overlap. Metrics to report: batch latency, cpu preprocessing latency, gpu kernel time, transfer time, GPU utilization, and peak GPU memory. These are sufficient to identify and act on the bottleneck.

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